1. Field of the Invention
The present invention generally relates to CCD (charge coupled device) delay lines and, more particularly, is directed to a CCD delay line which employs a floating gate (FG) or a floating diffusion gate at its intermediate output portion.
2. Description of the Prior Art
CCD delay lines are devices which make effective use of charge transfer and/or time operation function to delay or vary a signal from a timing standpoint, thereby processing a signal. The CCD delay line is different from a CCD image pickup element in that signal charges are calculated by an input signal voltage and injected while signal charges are generated and injected by the incidence of light according to the CCD image pickup element. A delay time (delay amount) Td of this CCD delay line is calculated by the following equation: EQU Td=N.times.1/fc
where N is the number of transfer stages and fc the sampling frequency.
In the case of the device in which the transfer stage N is 680 [bit] and the sampling frequency fc is 10.73 [MHz], the delay time Td thereof is expressed as: EQU Td=680.times.1/(10.73.times.10.sup.6)=63.4 [.mu.sec]
This delay time Td becomes substantially equal to the horizontal synchronizing frequency of a television signal. Further, if the sampling frequency fc is variable, then the delay time Td also becomes variable so that the signal can be compressed and/or expanded from a time base standpoint.
FIG. 1 is a cross-sectional view illustrating an example of a structure of a CCD delay line employing floating gate (FG) according to the prior art.
As shown in FIG. 1, a plurality of stages (n stages) of charge transfer units 3.sub.n, each formed of an electrode pair of a storage gate electrode 4 and a transfer gate electrode 5 are sequentially arrayed and at least one intermediate output portion 7 for deriving a signal of a predetermined delay time is provided to the rear stage of, for example, a (k-1)'th stage of an electric charge transfer section 3.sub.k-1 from the signal input side. In this case, regardless of the front and/or rear stage of the intermediate output portion 7, channel lengths and channel widths of the storage gate electrode 4 and the transfer gate electrode 5 are set to be the same. Further, the channel lengths of the storage gate electrode 4 and the transfer gate electrode 5 tend to be reduced as the CCD delay line becomes more and more densified.
However, if the channel lengths of the storage gate electrode 4 and the transfer gate electrode 5 of each of the charge transfer sections 3 are reduced as the CCD delay line becomes more and more densified, then when a potential becomes deep in the storage state of the intermediate output section 7 as shown by a solid line in FIG. 2, a potential barrier beneath the transfer electrode 5 in a charge transfer section 3.sub.k provided at the rear stage of the intermediate output portion 7 is affected in a three-dimensional fashion. As a consequence, an original potential shown by a one-dot chain line in FIG. 2 is changed as shown by the solid line so that a sufficient potential for transferring and storing all electric charges from the intermediate output section 7 cannot be secured.
In other words, while the CCD delay line is made more and more densified by reducing the channel lengths of the storage gate electrode 4 and the transfer gate electrode 5 of each of the charge transfer sections 3, the potential barrier under the transfer gate electrode 5 in the charge transfer section 3.sub.k provided at the rear stage of the intermediate output section 7 is changed by the influence of the potential at the front stage of the intermediate output section 7 so that the amount of the electric charges treated in the charge transfer section 3.sub.k provided at the rear stage of the intermediate output section 7 is reduced, thereby deteriorating the charge transfer efficiency.